1. Technical Field
The disclosed embodiments relate to the latching of incoming data, and more particularly to a delay line that automatically tracks the setup time of a latching element across PVT (process, supply voltage, temperature) variations.
2. Background Information
A high-speed input/output (I/O) interface between a processor device and a Double-Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) device is designed to accommodate the reading/writing of data on both the rising and falling edges of a strobe signal. The strobe signal is also referred to as a clock signal. Such a high-speed I/O interface should work reliably across process, voltage and temperature (PVT) variations given a small “data-valid” window. The data-valid window can be significantly less than a half-clock period of the strobe signal due to duty cycle distortion effects, timing uncertainties (jitter), and setup-hold requirements.
FIG. 1 (Prior Art) is a diagram of a high-speed I/O interface in the read path between a processor device 1 and a DDR SDRAM device 2. The incoming strobe signal DQS is nominally edge-aligned with the data signals D[7:0] received from the external DDR SDRAM. The strobe DQS and the data signals D[7:0] are edge-aligned to one another as these signals are received onto the processor device 1 that is reading the data from the DDR SDRAM device 2. A delay circuit is used to delay the incoming strobe signal DQS with respect to the incoming data D[7:0] by a time Tsd to produce a positive delayed strobe signal DQS_PE. Similarly, the delay circuit is used to delay the incoming strobe signal DQS with respect to the incoming data D[7:0] signals by time Tsd to produce a negative delayed strobe signal DQS_NE. The value of Tsd is such that the delayed strobes DQS_PE and DQS_NE fall in the data-valid window for a given operating frequency.
FIG. 2 (Prior Art) is a diagram that illustrates the DQS_PE and DQS_NE strobes, the delay time Tsd, and the data-valid windows. One technique that has been used to control the Tsd value involves use of a Calibrated Delay Circuit (CDC). The CDC involves a programmable delay array 3 in combination with a calibration engine 4. The CDC produces delay Tsd that is constant across PVT. Tsd is selected such that the delayed strobe DQS_PE is centered within a first data-valid window shown in FIG. 2. The DQS_PE strobe (the rising edge of DQS_PE) is therefore usable to latch in a first eight bits of data D[7:0] that is valid within the first data-valid window. The delayed strobe DQS_NE is similarly centered within a second data-valid window. The DQS_NE strobe (the rising edge of DQS_NE) is therefore usable to latch in a second eight bits of data D[7:0] that is valid within the second data valid-window. For a given temperature and supply voltage, the calibration engine determines the number of programmable delay array elements needed to produce Tsd. This information is conveyed to programmable delay array 3 in the form of a calibration code CAL_CODE[N:0]. In practice, the temperature of the circuit changes depending upon ambient conditions and the supply voltage is intentionally scaled up or scaled down depending on the usage mode of the processor. A scaled up supply voltage may, for example, be used in a high performance/high power usage mode, whereas a scaled down supply voltage may be used in a low performance/low power usage mode.
Such changes in temperature and supply voltage may cause the DQS_PE and DQS_NE strobes to deviate from their centered position within their respective data-valid windows, and may even cause the DQS_PE and DQS_NE strobes to fall outside their respective data-valid windows. This may result in memory access failures. This problem can be addressed by operating calibration engine 4 continuously and updating the programmable delay array 3 whenever there is a change in calibration code. However, this approach results in increased power consumption due to continuous operation of the calibration engine. Moreover, memory access operations have to be suspended whenever the calibration code is being updated, thereby reducing overall system performance due to associated memory latency.